? semiconductor components industries, llc, 2004 august, 2004 ? rev. 3 456 publication order number: ntd3055l170/d 9.0 amps, 60 volts, logic level, n ? channel dpak designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. features ? pb ? free packages are available typical applications ? power supplies ? converters ? power motor controls ? bridge circuits maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss 60 vdc drain ? to ? gate voltage (r gs = 10 m ) v dgr 60 vdc gate ? to ? source voltage ? continuous ? non ? repetitive (t p 10 ms) v gs v gs 15 20 vdc drain current ? continuous @ t a = 25 c ? continuous @ t a = 100 c ? single pulse (t p 10 s) i d i d i dm 9.0 3.0 27 adc apk total power dissipation @ t a = 25 c derate above 25 c total power dissipation @ t a = 25 c (note 1) total power dissipation @ t a = 25 c (note 2) p d 28.5 0.19 2.1 1.5 w w/ c w w operating and storage temperature range t j , t stg ? 55 to 175 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 5.0 vdc, l = 1.0 mh, i l (pk) = 7.75 a, v ds = 60 vdc) e as 30 mj thermal resistance ? junction ? to ? case ? junction ? to ? ambient (note 1) ? junction ? to ? ambient (note 2) r jc r ja r ja 5.2 71.4 100 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. when surface mounted to an fr4 board using 0.5 sq in pad size. 2. when surface mounted to an fr4 board using minimum recommended pad size. 9.0 amperes, 60 volts r ds(on) = 170 m n ? channel d s g dpak case 369aa (surface mounted) style 2 1 2 3 4 dpak ? 3 case 369d (straight lead) style 2 marking diagrams 1 gate 3 source 2 drain 4 drain ayw 3170l 1 gate 3 source 2 drain 4 drain ayw 3170l 3170l = device code a = assembly location y = year w = work week 1 2 3 4 see detailed ordering and shipping information in the package dimensions section on page 457 of this data sheet. ordering information http://onsemi.com
ntd3055l170 http://onsemi.com 457 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (note 3) (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 60 ? ? 53.6 ? ? vdc mv/ c zero gate voltage drain current (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 150 c) i dss ? ? ? ? 1.0 10 adc gate ? body leakage current (v gs = 15 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.7 4.2 2.0 ? vdc mv/ c static drain ? to ? source on ? resistance (note 3) (v gs = 5.0 vdc, i d = 4.5 adc) r ds(on) ? 153 170 m static drain ? to ? source on ? voltage (note 3) (v gs = 5.0 vdc, i d = 9.0 adc) (v gs = 5.0 vdc, i d = 4.5 adc, t j = 150 c) v ds(on) ? ? 1.8 1.3 2.1 ? vdc forward transconductance (note 3) (v ds = 8.0 vdc, i d = 6.0 adc) g fs ? 7.3 ? mhos dynamic characteristics input capacitance (v 25 vdc v 0 vdc c iss ? 195 275 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c oss ? 70 100 p transfer capacitance f = 1 . 0 mhz) c rss ? 29 42 switching characteristics (note 4) turn ? on delay time t d(on) ? 9.7 20 ns rise time (v dd = 30 vdc, i d = 9.0 adc, v gs = 5 0 vdc t r ? 69 150 turn ? off delay time v gs = 5.0 vdc, r g = 9.1 ) ( note 3 ) t d(off) ? 10 20 fall time r g = 9 . 1 ) (note 3) t f ? 38 80 gate charge (v 48 vdc i 9 0 adc q t ? 4.7 10 nc g (v ds = 48 vdc, i d = 9.0 adc, v gs = 5.0 vdc) (note 3) q 1 ? 1.4 ? v gs = 5 . 0 vdc) (note 3) q 2 ? 2.9 ? source ? drain diode characteristics forward on ? voltage (i s = 9.0 adc, v gs = 0 vdc) (note 3) (i s = 9.0 adc, v gs = 0 vdc, t j = 150 c) v sd ? ? 0.98 0.85 1.25 ? vdc reverse recovery time (i 9 0 adc v 0 vdc t rr ? 29.8 ? ns y (i s = 9.0 adc, v gs = 0 vdc, di s /dt = 100 a/ s) (note 3) t a ? 17.6 ? di s /dt = 100 a/ s) (note 3) t b ? 12.2 ? reverse recovery stored charge q rr ? 0.031 ? c 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures. ordering information device package shipping ? ntd3055l170 dpak 75 units/rail ntd3055l170g dpak (pb ? free) 75 units/rail ntd3055l170 ? 1 dpak ? 3 75 units/rail ntd3055l170 ? 1g dpak ? 3 (pb ? free) 75 units/rail NTD3055L170T4 dpak 2500 tape & reel NTD3055L170T4g dpak (pb ? free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd3055l170 http://onsemi.com 458 4 0.15 16 12 0.1 0.05 0 820 0.2 0.35 24 2.2 1.6 1.2 1.4 1 0.8 0.6 1 100 1000 08 8 2 1 v ds , drain ? to ? source voltage (volts) i d , drain current (amps) 0 v gs , gate ? to ? source voltage (volts) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (amps) 4 0.15 10 8 0.1 0.05 0 612 figure 3. on ? resistance versus gate ? to ? source voltage i d , drain current (amps) figure 4. on ? resistance versus drain current and gate voltage i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current versus voltage v ds , drain ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 20 ? 50 50 25 0 ? 25 75 125 100 1 2.5 6 040 30 20 60 10 3 4 12 8 v v ds 10 v t j = 25 c t j = ? 55 c t j = 100 c t j = 100 c v gs = 10 v v gs = 15 v 150 175 v gs = 0 v i d = 4.5 a v gs = 5 v 16 0.2 0.35 v gs = 10 v t j = 25 c t j = ? 55 c t j = 100 c 18 t j = 150 c t j = 100 c 4 0 16 8 12 3.5 4 t j = 25 c t j = ? 55 c 50 10 6 v 5 v 4 v 3.5 v 3 v 1.8 4567 1.5 2 3 4.5 5 5.5 0.25 0.3 14 16 0.25 0.3 2 t j = 125 c
ntd3055l170 http://onsemi.com 459 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain ? gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn ? on and turn ? off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off ? state condition when calculating t d(on) and is read at a voltage corresponding to the on ? state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is af fected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. c rss 10 0 10 15 20 25 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 700 200 0 v gs v ds 300 100 55 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 400 500 600
ntd3055l170 http://onsemi.com 460 10 0 0.6 drain ? to ? source diode characteristics v sd , source ? to ? drain voltage (volts) figure 8. gate ? to ? source and drain ? to ? source voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current v gs , gate ? to ? source voltage (volts) 0 5 3 1 0 q g , total gate charge (nc) 6 4 2 3 100 12 5 0.68 0.76 0.96 2 4 6 i d = 9 a t j = 25 c v gs q 2 q 1 q t t r t d(off) t d(on) t f 10 v ds = 30 v i d = 9 a v gs = 5 v 0.84 0.92 4 8 0.88 0.8 0.72 0.64 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain ? to ? source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off ? state and the on ? state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e ? fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy , avalanche energy capability is not a constant. the energy rating decreases non ? linearly with an increase of peak current in avalanche and peak junction temperature. although many e ? fets can withstand the stress of drain ? to ? source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
ntd3055l170 http://onsemi.com 461 safe operating area figure 11. maximum rated forward biased safe operating area t j , starting junction temperature ( c) e as , single pulse drain ? to ? source figure 12. maximum avalanche energy versus starting junction temperature 0.1 1 100 v ds , drain ? to ? source voltage (volts) figure 13. thermal response 100 avalanche energy (mj) i d , drain current (amps) 0.1 0 25 50 75 100 125 8 i d = 7.75 a 10 10 175 figure 14. diode reverse recovery waveform 16 32 v gs = 15 v single pulse t c = 25 c 1 ms 100 s 10 ms dc 10 s 150 24 r(t), effective transient thermal resistance (normalized) t, time ( s) 0.2 d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 0.1
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